Name: Soft Error Reliability of VLSI Circuits: Analysis and Mitigation Techniques (en Inglés)
Price: 269.35 PEN
Availability: InStock
Author: Ghavami, Behnam ; Raji, Mohsen
ISBN: 9783030516123

portada Soft Error Reliability of VLSI Circuits: Analysis and Mitigation Techniques (en Inglés)

Formato

Libro Físico

Autor

Behnam Ghavami

Mohsen Raji

Editorial

Springer

Idioma

Inglés

N° páginas

114

Encuadernación

Tapa Blanda

Dimensiones

23.4 x 15.6 x 0.7 cm

Peso

0.19 kg.

ISBN13

9783030516123

N° edición

Categorías

Cibernética y teoría de sistemas
Ingeniería eléctrica
Electrónica: circuitos y componentes

Soft Error Reliability of VLSI Circuits: Analysis and Mitigation Techniques (en Inglés)

Behnam Ghavami (Autor) · Mohsen Raji (Autor) · Springer · Tapa Blanda

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Origen: Estados Unidos (Costos de importación incluídos en el precio)

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Reseña del libro "Soft Error Reliability of VLSI Circuits: Analysis and Mitigation Techniques (en Inglés)"

This book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today's reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimationand GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques.