Name: Gain-Cell Embedded Drams for Low-Power VLSI Systems-On-Chip (en Inglés)
Price: 541.03 PEN
Availability: InStock
Author: Meinerzhagen, Pascal ; Teman, Adam ; Giterman, Robert
ISBN: 9783319868554

portada Gain-Cell Embedded Drams for Low-Power VLSI Systems-On-Chip (en Inglés)

Formato

Libro Físico

Autor

Pascal Meinerzhagen

Adam Teman

Robert Giterman

Editorial

Springer

Idioma

Inglés

N° páginas

146

Encuadernación

Tapa Blanda

Dimensiones

23.4 x 15.6 x 0.9 cm

Peso

0.23 kg.

ISBN13

9783319868554

N° edición

Categorías

Electrónica: circuitos y componentes
Hardware | soporte físico del ordenador

Gain-Cell Embedded Drams for Low-Power VLSI Systems-On-Chip (en Inglés)

Pascal Meinerzhagen (Autor) · Adam Teman (Autor) · Robert Giterman (Autor) · Springer · Tapa Blanda

Libro Nuevo

S/ 541,03

S/ 1.082,06

Ahorras: S/ 541,03

50% descuento

Cantidad
Estado: Nuevo

Envío normal

Origen: Estados Unidos (Costos de importación incluídos en el precio)

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Reseña del libro "Gain-Cell Embedded Drams for Low-Power VLSI Systems-On-Chip (en Inglés)"

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.